Capacitors are used in many types of semiconductor devices. Within memory devices, such as a dynamic-random-access memory (DRAM) cell or a nonvolatile-random-access memory (NVRAM) cell, the capacitor acts as a storage capacitor. Metal-oxide dielectric layers may be used in storage capacitors for the DRAM or NVRAM cells because the metal-oxide dielectric layers may have a high-permittivity or ferroelectric properties. As used in this specification, high-permittivity means a permittivity higher than the permittivity of silicon dioxide.
A limitation of capacitors with metal-oxide dielectric layers is the ability to integrate the formation of the capacitors into the process flow for semiconductor devices. A specific example using an NVRAM cell illustrates some of the problems. FIG. 1 includes a circuit diagram of an NVRAM cell 1 with a ferroelectric capacitor 2 and a transistor 3. One electrode of the ferroelectric capacitor 2 is coupled to the drive line (DL), and the other electrode is coupled to a source/drain region of the transistor 3. The transistor 3 further includes another source/drain region coupled to a bit line (BL) and a gate electrode coupled to a word line (WL).
One prior art NVRAM cell includes a "stacked" ferroelectric capacitor. In this NVRAM cell, the transistor is formed in the substrate, a conductive plug is formed to a source/drain region of the transistor, and the ferroelectric capacitor is formed over the conductive plug. An integration problem is the presence of the conductive plug while the ferroelectric capacitor is formed. Many types of conductive plugs include silicon or a metal-containing material. A metal-oxide layer that forms the dielectric layer for the ferroelectric capacitor typically must be oxidized at a temperature higher than about 500 degrees Celsius in order for the metal-oxide layer to have ferroelectric properties. As used in this specification, high temperature means a temperature higher than about 500 degrees Celsius. The conductive plug may not be able to withstand such a processing step. For example, the plug may oxidize to form a region of poor conductivity, thus degrading, or even eliminating, the electrical path between the electrode and the source/drain region of the underlying transistor. As a further example, metal from a metal-containing material may diffuse into the substrate. The material of the conductive plug may either form a junction spike or a silicide material that extends completely through the source/drain region causing and electrical short between one of the electrodes of the ferroelectric capacitor and the substrate or a well region. The use of barrier layers should not help because most barrier layers cannot withstand processing higher than about 500 degrees Celsius.
In one NVRAM cell, a metal strap may be formed between an electrode of the ferroelectric layer and a source/drain region after the ferroelectric capacitor has been formed. FIG. 2 includes a plan view of a "strapped" NVRAM cell 90 that includes a transistor 93 and a ferroelectric capacitor 95. A metal conductor 91 acts as a bit line for the NVRAM cell 90 and is electrically connected to a first doped region 931 that acts as a source/drain region by a contact 911. Conductive member 92 acts as a gate electrode for transistor 93 and is part of the word line. A second doped region 932 acts as the other source/drain region for the transistor 93 and lies on the other side of the conductive member 92. The active region of transistor 93 is defined by field isolation region 98.
A first dielectric layer (not shown) is formed after the transistor 93 is formed and before forming the ferroelectric capacitor 95. Most of the ferroelectric capacitor 95 is typically formed over the field isolation region 98. The ferroelectric capacitor 95 includes a lower electrode layer 96 that acts as a drive line, a metal-oxide dielectric layer (not shown) that acts as the ferroelectric dielectric, and an upper electrode layer 97. A second insulating layer (not shown) is formed over the cell 90. Conductive member 94 electrically connects the upper electrode layer 97 of the ferroelectric capacitor 95 with the second doped region 932. Dashed lines that appear in metal conductor 91 and conductive member 94 show where some of the underlying elements of the cell lie below the metal conductor 91 or the conductive member 94. At least one insulating layer lies between the metal conductor 91 or conductive member 94 and those underlying elements indicated by dashed lines. It should be noted that contacts 941, 942, and 911 are typically formed during the same processing steps and that the contacts extend at least through the second insulating layer. It is further noted that the conductive members 91 and 94 are typically formed during the same processing steps, too.
NVRAM cell 90 is very large. The cell size is limited by how close the conductive members 91 and 94 may be placed to each other and/or how close contacts 941, 942, and 911 may be placed to one another. Further, the cell size is kept large because the orientation of the bit lines across the array typically are generally perpendicular to conductive member 92 that acts as the word line. Thus, the length of the conductive member 91 that acts as the bit line for the cell is generally parallel with the conductive member 94 that acts as an electrical strap. Essentially, the transistor and ferroelectric capacitor are formed side by side from a plan view. The ferroelectric capacitor overlies little, if any, of the transistor because enough tolerance must be given, so that contact 942 contacts doped region 932 and does not contact the lower or upper electrode layer 96 of the ferroelectric capacitor 95.
Similar problems occur with other NVRAM cells, such as those shown in FIGS. 3 and 4. FIG. 3 is a circuit diagram of an NVRAM cell 30 that includes two transistors 31 and 33 and two ferroelectric capacitors 32 and 34. One difference between NVRAM cell 30 and NVRAM cell 1 is the use of complementary bit lines (BL and BL) as opposed to a single bit line (BL). FIG. 4 includes a circuit diagram of NVRAM cell 40 that includes two p-channel transistors 47 and 44, two n-channel transistors 42 and 45, and two ferroelectric capacitors 43 and 46. A difference between this cell and NVRAM cell 1 is the use of complementary bit lines (BL and BL) and complementary word lines (WL and WL). Stacked ferroelectric capacitors used in NVRAM cells 30 and 40 would have process integration problems, and strapped cells would occupy too much substrate area.
FIG. 5 includes a circuit diagram of a DRAM cell 50. Circuit diagrams for a DRAM cell 50 and NVRAM cell 90 are similar. The DRAM cell 50 includes a transistor 55 and a storage capacitor 56. A bit line (BL) is coupled to a source/drain region of transistor 55. Transistor 55 further includes a gate electrode that is coupled to a word line (WL) and another source/drain region that is coupled to one of the electrodes of the capacitor 56. The other electrode of the capacitor 56 is coupled to a constant voltage source V.sub.C. V.sub.C for the cell 50 may be V.sub.SS or half the potential of V.sub.DD.
Smaller design rules may limit the amount of capacitance that can be stored by the storage capacitor of the DRAM cell. One way to increase the capacitance of the storage capacitor without increasing thicknesses or dimensions is the use of a high-permittivity dielectric material, such as a metal-oxide dielectric material. Unfortunately, a storage capacitor with metal-oxide dielectric layer suffers from integration problems similar to the NVRAM cell. Many of the integration problems of metal-oxide dielectric layers are not seen with a conventional silicon-containing dielectric material, such as silicon dioxide and silicon nitride.